Linux sh52.ich-4.com 5.14.0-611.26.1.el9_7.x86_64 #1 SMP PREEMPT_DYNAMIC Thu Jan 29 05:24:47 EST 2026 x86_64
LiteSpeed
Server IP : 198.143.147.58 & Your IP : 216.73.217.21
Domains :
Cant Read [ /etc/named.conf ]
User : actualbuzz
Terminal
Auto Root
Create File
Create Folder
Localroot Suggester
Backdoor Destroyer
Readme
/
lib /
clang /
20 /
include /
Delete
Unzip
Name
Size
Permission
Date
Action
cuda_wrappers
[ DIR ]
drwxr-xr-x
2026-02-03 15:09
fuzzer
[ DIR ]
drwxr-xr-x
2026-02-03 15:08
llvm_libc_wrappers
[ DIR ]
drwxr-xr-x
2026-02-03 15:09
llvm_offload_wrappers
[ DIR ]
drwxr-xr-x
2026-02-03 15:09
openmp_wrappers
[ DIR ]
drwxr-xr-x
2026-02-03 15:09
orc
[ DIR ]
drwxr-xr-x
2026-02-03 15:08
ppc_wrappers
[ DIR ]
drwxr-xr-x
2026-02-03 15:09
profile
[ DIR ]
drwxr-xr-x
2026-02-03 15:08
sanitizer
[ DIR ]
drwxr-xr-x
2026-02-03 15:08
xray
[ DIR ]
drwxr-xr-x
2026-02-03 15:08
zos_wrappers
[ DIR ]
drwxr-xr-x
2026-02-03 15:09
__clang_cuda_builtin_vars.h
4.78
KB
-rw-r--r--
2025-07-08 23:06
__clang_cuda_cmath.h
18.06
KB
-rw-r--r--
2025-07-08 23:06
__clang_cuda_complex_builtins.h
9.36
KB
-rw-r--r--
2025-07-08 23:06
__clang_cuda_device_functions.h
57.36
KB
-rw-r--r--
2025-07-08 23:06
__clang_cuda_intrinsics.h
29.87
KB
-rw-r--r--
2025-07-08 23:06
__clang_cuda_libdevice_declares.h
21.89
KB
-rw-r--r--
2025-07-08 23:06
__clang_cuda_math.h
16.21
KB
-rw-r--r--
2025-07-08 23:06
__clang_cuda_math_forward_declares.h
8.27
KB
-rw-r--r--
2025-07-08 23:06
__clang_cuda_runtime_wrapper.h
17.6
KB
-rw-r--r--
2025-07-08 23:06
__clang_cuda_texture_intrinsics.h
31.86
KB
-rw-r--r--
2025-07-08 23:06
__clang_hip_cmath.h
26.48
KB
-rw-r--r--
2025-07-08 23:06
__clang_hip_libdevice_declares.h
19.87
KB
-rw-r--r--
2025-07-08 23:06
__clang_hip_math.h
32.78
KB
-rw-r--r--
2025-07-08 23:06
__clang_hip_runtime_wrapper.h
4.94
KB
-rw-r--r--
2025-07-08 23:06
__clang_hip_stdlib.h
1.19
KB
-rw-r--r--
2025-07-08 23:06
__stdarg___gnuc_va_list.h
467
B
-rw-r--r--
2025-07-08 23:06
__stdarg___va_copy.h
445
B
-rw-r--r--
2025-07-08 23:06
__stdarg_header_macro.h
417
B
-rw-r--r--
2025-07-08 23:06
__stdarg_va_arg.h
793
B
-rw-r--r--
2025-07-08 23:06
__stdarg_va_copy.h
451
B
-rw-r--r--
2025-07-08 23:06
__stdarg_va_list.h
448
B
-rw-r--r--
2025-07-08 23:06
__stddef_header_macro.h
417
B
-rw-r--r--
2025-07-08 23:06
__stddef_max_align_t.h
857
B
-rw-r--r--
2025-07-08 23:06
__stddef_null.h
875
B
-rw-r--r--
2025-07-08 23:06
__stddef_nullptr_t.h
958
B
-rw-r--r--
2025-07-08 23:06
__stddef_offsetof.h
708
B
-rw-r--r--
2025-07-08 23:06
__stddef_ptrdiff_t.h
717
B
-rw-r--r--
2025-07-08 23:06
__stddef_rsize_t.h
710
B
-rw-r--r--
2025-07-08 23:06
__stddef_size_t.h
708
B
-rw-r--r--
2025-07-08 23:06
__stddef_unreachable.h
735
B
-rw-r--r--
2025-07-08 23:06
__stddef_wchar_t.h
853
B
-rw-r--r--
2025-07-08 23:06
__stddef_wint_t.h
443
B
-rw-r--r--
2025-07-08 23:06
__wmmintrin_aes.h
5.15
KB
-rw-r--r--
2025-07-08 23:06
__wmmintrin_pclmul.h
1.99
KB
-rw-r--r--
2025-07-08 23:06
adcintrin.h
5.43
KB
-rw-r--r--
2025-07-08 23:06
adxintrin.h
3.37
KB
-rw-r--r--
2025-07-08 23:06
altivec.h
698.45
KB
-rw-r--r--
2025-07-08 23:06
amdgpuintrin.h
7.4
KB
-rw-r--r--
2025-07-08 23:06
ammintrin.h
7.56
KB
-rw-r--r--
2025-07-08 23:06
amxavx512intrin.h
12.67
KB
-rw-r--r--
2025-07-08 23:06
amxbf16transposeintrin.h
3.44
KB
-rw-r--r--
2025-07-08 23:06
amxcomplexintrin.h
6.81
KB
-rw-r--r--
2025-07-08 23:06
amxcomplextransposeintrin.h
11.78
KB
-rw-r--r--
2025-07-08 23:06
amxfp16intrin.h
3.25
KB
-rw-r--r--
2025-07-08 23:06
amxfp16transposeintrin.h
3.44
KB
-rw-r--r--
2025-07-08 23:06
amxfp8intrin.h
8.63
KB
-rw-r--r--
2025-07-08 23:06
amxintrin.h
19.83
KB
-rw-r--r--
2025-07-08 23:06
amxmovrsintrin.h
2.24
KB
-rw-r--r--
2025-07-08 23:06
amxmovrstransposeintrin.h
9.18
KB
-rw-r--r--
2025-07-08 23:06
amxtf32intrin.h
3.48
KB
-rw-r--r--
2025-07-08 23:06
amxtf32transposeintrin.h
3.56
KB
-rw-r--r--
2025-07-08 23:06
amxtransposeintrin.h
10.6
KB
-rw-r--r--
2025-07-08 23:06
arm64intr.h
993
B
-rw-r--r--
2025-07-08 23:06
arm_acle.h
29.97
KB
-rw-r--r--
2025-07-08 23:06
arm_bf16.h
548
B
-rw-r--r--
2025-09-17 20:10
arm_cde.h
32.67
KB
-rw-r--r--
2025-09-17 20:10
arm_cmse.h
6.21
KB
-rw-r--r--
2025-07-08 23:06
arm_fp16.h
16.94
KB
-rw-r--r--
2025-09-17 20:10
arm_mve.h
1.48
MB
-rw-r--r--
2025-09-17 20:10
arm_neon.h
2.66
MB
-rw-r--r--
2025-09-17 20:10
arm_neon_sve_bridge.h
9.48
KB
-rw-r--r--
2025-07-08 23:06
arm_sme.h
223.36
KB
-rw-r--r--
2025-09-17 20:10
arm_sve.h
2.03
MB
-rw-r--r--
2025-09-17 20:10
arm_vector_types.h
9.86
KB
-rw-r--r--
2025-09-17 20:10
armintr.h
843
B
-rw-r--r--
2025-07-08 23:06
avx10_2_512bf16intrin.h
22.87
KB
-rw-r--r--
2025-07-08 23:06
avx10_2_512convertintrin.h
12.88
KB
-rw-r--r--
2025-07-08 23:06
avx10_2_512minmaxintrin.h
7.35
KB
-rw-r--r--
2025-07-08 23:06
avx10_2_512niintrin.h
13.71
KB
-rw-r--r--
2025-07-08 23:06
avx10_2_512satcvtdsintrin.h
13.48
KB
-rw-r--r--
2025-07-08 23:06
avx10_2_512satcvtintrin.h
16.6
KB
-rw-r--r--
2025-07-08 23:06
avx10_2bf16intrin.h
43.63
KB
-rw-r--r--
2025-07-08 23:06
avx10_2convertintrin.h
22.75
KB
-rw-r--r--
2025-07-08 23:06
avx10_2copyintrin.h
2.35
KB
-rw-r--r--
2025-07-08 23:06
avx10_2minmaxintrin.h
13.53
KB
-rw-r--r--
2025-07-08 23:06
avx10_2niintrin.h
16.6
KB
-rw-r--r--
2025-07-08 23:06
avx10_2satcvtdsintrin.h
15.36
KB
-rw-r--r--
2025-07-08 23:06
avx10_2satcvtintrin.h
18.87
KB
-rw-r--r--
2025-07-08 23:06
avx2intrin.h
188.12
KB
-rw-r--r--
2025-07-08 23:06
avx512bf16intrin.h
10.58
KB
-rw-r--r--
2025-07-08 23:06
avx512bitalgintrin.h
2.56
KB
-rw-r--r--
2025-07-08 23:06
avx512bwintrin.h
76.02
KB
-rw-r--r--
2025-07-08 23:06
avx512cdintrin.h
4.23
KB
-rw-r--r--
2025-07-08 23:06
avx512dqintrin.h
58.87
KB
-rw-r--r--
2025-07-08 23:06
avx512fintrin.h
383.45
KB
-rw-r--r--
2025-07-08 23:06
avx512fp16intrin.h
156.92
KB
-rw-r--r--
2025-07-08 23:06
avx512ifmaintrin.h
2.6
KB
-rw-r--r--
2025-07-08 23:06
avx512ifmavlintrin.h
4.6
KB
-rw-r--r--
2025-07-08 23:06
avx512vbmi2intrin.h
13.18
KB
-rw-r--r--
2025-07-08 23:06
avx512vbmiintrin.h
3.83
KB
-rw-r--r--
2025-07-08 23:06
avx512vbmivlintrin.h
7.23
KB
-rw-r--r--
2025-07-08 23:06
avx512vlbf16intrin.h
19.46
KB
-rw-r--r--
2025-07-08 23:06
avx512vlbitalgintrin.h
4.52
KB
-rw-r--r--
2025-07-08 23:06
avx512vlbwintrin.h
121.56
KB
-rw-r--r--
2025-07-08 23:06
avx512vlcdintrin.h
7.95
KB
-rw-r--r--
2025-07-08 23:06
avx512vldqintrin.h
46.71
KB
-rw-r--r--
2025-07-08 23:06
avx512vlfp16intrin.h
85.51
KB
-rw-r--r--
2025-07-08 23:06
avx512vlintrin.h
322.6
KB
-rw-r--r--
2025-07-08 23:06
avx512vlvbmi2intrin.h
26.01
KB
-rw-r--r--
2025-07-08 23:06
avx512vlvnniintrin.h
13.41
KB
-rw-r--r--
2025-07-08 23:06
avx512vlvp2intersectintrin.h
4.67
KB
-rw-r--r--
2025-07-08 23:06
avx512vnniintrin.h
4.32
KB
-rw-r--r--
2025-07-08 23:06
avx512vp2intersectintrin.h
3.03
KB
-rw-r--r--
2025-07-08 23:06
avx512vpopcntdqintrin.h
2.3
KB
-rw-r--r--
2025-07-08 23:06
avx512vpopcntdqvlintrin.h
3.86
KB
-rw-r--r--
2025-07-08 23:06
avxifmaintrin.h
5.75
KB
-rw-r--r--
2025-07-08 23:06
avxintrin.h
197.12
KB
-rw-r--r--
2025-07-08 23:06
avxneconvertintrin.h
14.09
KB
-rw-r--r--
2025-07-08 23:06
avxvnniint16intrin.h
15.84
KB
-rw-r--r--
2025-07-08 23:06
avxvnniint8intrin.h
17.02
KB
-rw-r--r--
2025-07-08 23:06
avxvnniintrin.h
10.44
KB
-rw-r--r--
2025-07-08 23:06
bmi2intrin.h
7.37
KB
-rw-r--r--
2025-07-08 23:06
bmiintrin.h
20.02
KB
-rw-r--r--
2025-07-08 23:06
builtins.h
846
B
-rw-r--r--
2025-07-08 23:06
cet.h
1.49
KB
-rw-r--r--
2025-07-08 23:06
cetintrin.h
3.27
KB
-rw-r--r--
2025-07-08 23:06
cldemoteintrin.h
1.18
KB
-rw-r--r--
2025-07-08 23:06
clflushoptintrin.h
1.17
KB
-rw-r--r--
2025-07-08 23:06
clwbintrin.h
1.2
KB
-rw-r--r--
2025-07-08 23:06
clzerointrin.h
1.19
KB
-rw-r--r--
2025-07-08 23:06
cmpccxaddintrin.h
2.33
KB
-rw-r--r--
2025-07-08 23:06
cpuid.h
11.9
KB
-rw-r--r--
2025-07-08 23:06
crc32intrin.h
3.27
KB
-rw-r--r--
2025-07-08 23:06
emmintrin.h
196.89
KB
-rw-r--r--
2025-07-08 23:06
enqcmdintrin.h
2.12
KB
-rw-r--r--
2025-07-08 23:06
f16cintrin.h
5.39
KB
-rw-r--r--
2025-07-08 23:06
float.h
6.43
KB
-rw-r--r--
2025-07-08 23:06
fma4intrin.h
6.82
KB
-rw-r--r--
2025-07-08 23:06
fmaintrin.h
28.65
KB
-rw-r--r--
2025-07-08 23:06
fxsrintrin.h
2.82
KB
-rw-r--r--
2025-07-08 23:06
gfniintrin.h
9.59
KB
-rw-r--r--
2025-07-08 23:06
gpuintrin.h
9.07
KB
-rw-r--r--
2025-07-08 23:06
hexagon_circ_brev_intrinsics.h
15.59
KB
-rw-r--r--
2025-07-08 23:06
hexagon_protos.h
374.42
KB
-rw-r--r--
2025-07-08 23:06
hexagon_types.h
130.38
KB
-rw-r--r--
2025-07-08 23:06
hresetintrin.h
1.36
KB
-rw-r--r--
2025-07-08 23:06
htmintrin.h
6.14
KB
-rw-r--r--
2025-07-08 23:06
htmxlintrin.h
9.01
KB
-rw-r--r--
2025-07-08 23:06
hvx_hexagon_protos.h
275.18
KB
-rw-r--r--
2025-07-08 23:06
ia32intrin.h
25.38
KB
-rw-r--r--
2025-07-08 23:06
immintrin.h
25.46
KB
-rw-r--r--
2025-07-08 23:06
intrin.h
18.16
KB
-rw-r--r--
2025-07-08 23:06
intrin0.h
13.76
KB
-rw-r--r--
2025-07-08 23:06
inttypes.h
2.37
KB
-rw-r--r--
2025-07-08 23:06
invpcidintrin.h
764
B
-rw-r--r--
2025-07-08 23:06
iso646.h
763
B
-rw-r--r--
2025-07-08 23:06
keylockerintrin.h
17.85
KB
-rw-r--r--
2025-07-08 23:06
larchintrin.h
8.5
KB
-rw-r--r--
2025-07-08 23:06
lasxintrin.h
142.14
KB
-rw-r--r--
2025-07-08 23:06
limits.h
3.71
KB
-rw-r--r--
2025-07-08 23:06
lsxintrin.h
134.7
KB
-rw-r--r--
2025-07-08 23:06
lwpintrin.h
5
KB
-rw-r--r--
2025-07-08 23:06
lzcntintrin.h
3.45
KB
-rw-r--r--
2025-07-08 23:06
mm3dnow.h
729
B
-rw-r--r--
2025-07-08 23:06
mm_malloc.h
1.88
KB
-rw-r--r--
2025-07-08 23:06
mmintrin.h
58.6
KB
-rw-r--r--
2025-07-08 23:06
module.modulemap
6.47
KB
-rw-r--r--
2025-07-08 23:06
movdirintrin.h
1.57
KB
-rw-r--r--
2025-07-08 23:06
movrs_avx10_2_512intrin.h
3.88
KB
-rw-r--r--
2025-07-08 23:06
movrs_avx10_2intrin.h
6.87
KB
-rw-r--r--
2025-07-08 23:06
movrsintrin.h
1.98
KB
-rw-r--r--
2025-07-08 23:06
msa.h
25.01
KB
-rw-r--r--
2025-07-08 23:06
mwaitxintrin.h
2.19
KB
-rw-r--r--
2025-07-08 23:06
nmmintrin.h
709
B
-rw-r--r--
2025-07-08 23:06
nvptxintrin.h
7.42
KB
-rw-r--r--
2025-07-08 23:06
omp-tools.h
50.86
KB
-rw-r--r--
2025-09-17 20:37
omp.h
23.36
KB
-rw-r--r--
2025-09-17 20:37
ompt-multiplex.h
51.11
KB
-rw-r--r--
2025-07-08 23:06
ompt.h
50.86
KB
-rw-r--r--
2025-09-17 20:37
ompx.h
7.38
KB
-rw-r--r--
2025-09-17 20:37
opencl-c-base.h
30.94
KB
-rw-r--r--
2025-07-08 23:06
opencl-c.h
874.98
KB
-rw-r--r--
2025-07-08 23:06
pconfigintrin.h
1.19
KB
-rw-r--r--
2025-07-08 23:06
pkuintrin.h
934
B
-rw-r--r--
2025-07-08 23:06
pmmintrin.h
11.12
KB
-rw-r--r--
2025-07-08 23:06
popcntintrin.h
1.9
KB
-rw-r--r--
2025-07-08 23:06
prfchiintrin.h
2.02
KB
-rw-r--r--
2025-07-08 23:06
prfchwintrin.h
2.06
KB
-rw-r--r--
2025-07-08 23:06
ptrauth.h
15.61
KB
-rw-r--r--
2025-07-08 23:06
ptwriteintrin.h
1.05
KB
-rw-r--r--
2025-07-08 23:06
raointintrin.h
6.59
KB
-rw-r--r--
2025-07-08 23:06
rdpruintrin.h
1.59
KB
-rw-r--r--
2025-07-08 23:06
rdseedintrin.h
2.85
KB
-rw-r--r--
2025-07-08 23:06
riscv_bitmanip.h
5.59
KB
-rw-r--r--
2025-07-08 23:06
riscv_corev_alu.h
3.94
KB
-rw-r--r--
2025-07-08 23:06
riscv_crypto.h
5.09
KB
-rw-r--r--
2025-07-08 23:06
riscv_ntlh.h
744
B
-rw-r--r--
2025-07-08 23:06
riscv_vector.h
17.11
KB
-rw-r--r--
2025-09-17 20:11
rtmintrin.h
1.25
KB
-rw-r--r--
2025-07-08 23:06
s390intrin.h
604
B
-rw-r--r--
2025-07-08 23:06
serializeintrin.h
881
B
-rw-r--r--
2025-07-08 23:06
sgxintrin.h
1.77
KB
-rw-r--r--
2025-07-08 23:06
sha512intrin.h
5.95
KB
-rw-r--r--
2025-07-08 23:06
shaintrin.h
7.37
KB
-rw-r--r--
2025-07-08 23:06
sifive_vector.h
6.88
KB
-rw-r--r--
2025-07-08 23:06
sm3intrin.h
7.29
KB
-rw-r--r--
2025-07-08 23:06
sm4evexintrin.h
1.17
KB
-rw-r--r--
2025-07-08 23:06
sm4intrin.h
8.2
KB
-rw-r--r--
2025-07-08 23:06
smmintrin.h
99.34
KB
-rw-r--r--
2025-07-08 23:06
stdalign.h
756
B
-rw-r--r--
2025-07-08 23:06
stdarg.h
2.44
KB
-rw-r--r--
2025-07-08 23:06
stdatomic.h
8.46
KB
-rw-r--r--
2025-07-08 23:06
stdbool.h
1.14
KB
-rw-r--r--
2025-07-08 23:06
stdckdint.h
1.63
KB
-rw-r--r--
2025-07-08 23:06
stddef.h
4.93
KB
-rw-r--r--
2025-07-08 23:06
stdint.h
30.33
KB
-rw-r--r--
2025-07-08 23:06
stdnoreturn.h
1.29
KB
-rw-r--r--
2025-07-08 23:06
tbmintrin.h
3.42
KB
-rw-r--r--
2025-07-08 23:06
tgmath.h
29.68
KB
-rw-r--r--
2025-07-08 23:06
tmmintrin.h
31.18
KB
-rw-r--r--
2025-07-08 23:06
tsxldtrkintrin.h
1.97
KB
-rw-r--r--
2025-07-08 23:06
uintrintrin.h
4.96
KB
-rw-r--r--
2025-07-08 23:06
unwind.h
11.21
KB
-rw-r--r--
2025-07-08 23:06
usermsrintrin.h
1.54
KB
-rw-r--r--
2025-07-08 23:06
vadefs.h
1.39
KB
-rw-r--r--
2025-07-08 23:06
vaesintrin.h
2.61
KB
-rw-r--r--
2025-07-08 23:06
varargs.h
584
B
-rw-r--r--
2025-07-08 23:06
vecintrin.h
419.23
KB
-rw-r--r--
2025-07-08 23:06
velintrin.h
2.1
KB
-rw-r--r--
2025-07-08 23:06
velintrin_approx.h
3.54
KB
-rw-r--r--
2025-07-08 23:06
velintrin_gen.h
69.06
KB
-rw-r--r--
2025-07-08 23:06
vpclmulqdqintrin.h
1.06
KB
-rw-r--r--
2025-07-08 23:06
waitpkgintrin.h
1.33
KB
-rw-r--r--
2025-07-08 23:06
wasm_simd128.h
81.71
KB
-rw-r--r--
2025-07-08 23:06
wbnoinvdintrin.h
749
B
-rw-r--r--
2025-07-08 23:06
wmmintrin.h
659
B
-rw-r--r--
2025-07-08 23:06
x86gprintrin.h
2.22
KB
-rw-r--r--
2025-07-08 23:06
x86intrin.h
1.38
KB
-rw-r--r--
2025-07-08 23:06
xmmintrin.h
117.43
KB
-rw-r--r--
2025-07-08 23:06
xopintrin.h
19.96
KB
-rw-r--r--
2025-07-08 23:06
xsavecintrin.h
2.51
KB
-rw-r--r--
2025-07-08 23:06
xsaveintrin.h
1.64
KB
-rw-r--r--
2025-07-08 23:06
xsaveoptintrin.h
1
KB
-rw-r--r--
2025-07-08 23:06
xsavesintrin.h
1.24
KB
-rw-r--r--
2025-07-08 23:06
xtestintrin.h
873
B
-rw-r--r--
2025-07-08 23:06
yvals_core.h
687
B
-rw-r--r--
2025-07-08 23:06
Save
Rename
/*===---- arm_fp16.h - ARM FP16 intrinsics ---------------------------------=== * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell * copies of the Software, and to permit persons to whom the Software is * furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included in * all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN * THE SOFTWARE. * *===-----------------------------------------------------------------------=== */ #ifndef __ARM_FP16_H #define __ARM_FP16_H #include <stdint.h> typedef __fp16 float16_t; #define __ai static __inline__ __attribute__((__always_inline__, __nodebug__)) #if defined(__aarch64__) || defined(__arm64ec__) #define vabdh_f16(__p0, __p1) __extension__ ({ \ float16_t __ret; \ float16_t __s0 = __p0; \ float16_t __s1 = __p1; \ __ret = (float16_t) __builtin_neon_vabdh_f16(__s0, __s1); \ __ret; \ }) #define vabsh_f16(__p0) __extension__ ({ \ float16_t __ret; \ float16_t __s0 = __p0; \ __ret = (float16_t) __builtin_neon_vabsh_f16(__s0); \ __ret; \ }) #define vaddh_f16(__p0, __p1) __extension__ ({ \ float16_t __ret; \ float16_t __s0 = __p0; \ float16_t __s1 = __p1; \ __ret = (float16_t) __builtin_neon_vaddh_f16(__s0, __s1); \ __ret; \ }) #define vcageh_f16(__p0, __p1) __extension__ ({ \ uint16_t __ret; \ float16_t __s0 = __p0; \ float16_t __s1 = __p1; \ __ret = (uint16_t) __builtin_neon_vcageh_f16(__s0, __s1); \ __ret; \ }) #define vcagth_f16(__p0, __p1) __extension__ ({ \ uint16_t __ret; \ float16_t __s0 = __p0; \ float16_t __s1 = __p1; \ __ret = (uint16_t) __builtin_neon_vcagth_f16(__s0, __s1); \ __ret; \ }) #define vcaleh_f16(__p0, __p1) __extension__ ({ \ uint16_t __ret; \ float16_t __s0 = __p0; \ float16_t __s1 = __p1; \ __ret = (uint16_t) __builtin_neon_vcaleh_f16(__s0, __s1); \ __ret; \ }) #define vcalth_f16(__p0, __p1) __extension__ ({ \ uint16_t __ret; \ float16_t __s0 = __p0; \ float16_t __s1 = __p1; \ __ret = (uint16_t) __builtin_neon_vcalth_f16(__s0, __s1); \ __ret; \ }) #define vceqh_f16(__p0, __p1) __extension__ ({ \ uint16_t __ret; \ float16_t __s0 = __p0; \ float16_t __s1 = __p1; \ __ret = (uint16_t) __builtin_neon_vceqh_f16(__s0, __s1); \ __ret; \ }) #define vceqzh_f16(__p0) __extension__ ({ \ uint16_t __ret; \ float16_t __s0 = __p0; \ __ret = (uint16_t) __builtin_neon_vceqzh_f16(__s0); \ __ret; \ }) #define vcgeh_f16(__p0, __p1) __extension__ ({ \ uint16_t __ret; \ float16_t __s0 = __p0; \ float16_t __s1 = __p1; \ __ret = (uint16_t) __builtin_neon_vcgeh_f16(__s0, __s1); \ __ret; \ }) #define vcgezh_f16(__p0) __extension__ ({ \ uint16_t __ret; \ float16_t __s0 = __p0; \ __ret = (uint16_t) __builtin_neon_vcgezh_f16(__s0); \ __ret; \ }) #define vcgth_f16(__p0, __p1) __extension__ ({ \ uint16_t __ret; \ float16_t __s0 = __p0; \ float16_t __s1 = __p1; \ __ret = (uint16_t) __builtin_neon_vcgth_f16(__s0, __s1); \ __ret; \ }) #define vcgtzh_f16(__p0) __extension__ ({ \ uint16_t __ret; \ float16_t __s0 = __p0; \ __ret = (uint16_t) __builtin_neon_vcgtzh_f16(__s0); \ __ret; \ }) #define vcleh_f16(__p0, __p1) __extension__ ({ \ uint16_t __ret; \ float16_t __s0 = __p0; \ float16_t __s1 = __p1; \ __ret = (uint16_t) __builtin_neon_vcleh_f16(__s0, __s1); \ __ret; \ }) #define vclezh_f16(__p0) __extension__ ({ \ uint16_t __ret; \ float16_t __s0 = __p0; \ __ret = (uint16_t) __builtin_neon_vclezh_f16(__s0); \ __ret; \ }) #define vclth_f16(__p0, __p1) __extension__ ({ \ uint16_t __ret; \ float16_t __s0 = __p0; \ float16_t __s1 = __p1; \ __ret = (uint16_t) __builtin_neon_vclth_f16(__s0, __s1); \ __ret; \ }) #define vcltzh_f16(__p0) __extension__ ({ \ uint16_t __ret; \ float16_t __s0 = __p0; \ __ret = (uint16_t) __builtin_neon_vcltzh_f16(__s0); \ __ret; \ }) #define vcvth_n_s16_f16(__p0, __p1) __extension__ ({ \ int16_t __ret; \ float16_t __s0 = __p0; \ __ret = (int16_t) __builtin_neon_vcvth_n_s16_f16(__s0, __p1); \ __ret; \ }) #define vcvth_n_s32_f16(__p0, __p1) __extension__ ({ \ int32_t __ret; \ float16_t __s0 = __p0; \ __ret = (int32_t) __builtin_neon_vcvth_n_s32_f16(__s0, __p1); \ __ret; \ }) #define vcvth_n_s64_f16(__p0, __p1) __extension__ ({ \ int64_t __ret; \ float16_t __s0 = __p0; \ __ret = (int64_t) __builtin_neon_vcvth_n_s64_f16(__s0, __p1); \ __ret; \ }) #define vcvth_n_u16_f16(__p0, __p1) __extension__ ({ \ uint16_t __ret; \ float16_t __s0 = __p0; \ __ret = (uint16_t) __builtin_neon_vcvth_n_u16_f16(__s0, __p1); \ __ret; \ }) #define vcvth_n_u32_f16(__p0, __p1) __extension__ ({ \ uint32_t __ret; \ float16_t __s0 = __p0; \ __ret = (uint32_t) __builtin_neon_vcvth_n_u32_f16(__s0, __p1); \ __ret; \ }) #define vcvth_n_u64_f16(__p0, __p1) __extension__ ({ \ uint64_t __ret; \ float16_t __s0 = __p0; \ __ret = (uint64_t) __builtin_neon_vcvth_n_u64_f16(__s0, __p1); \ __ret; \ }) #define vcvth_s16_f16(__p0) __extension__ ({ \ int16_t __ret; \ float16_t __s0 = __p0; \ __ret = (int16_t) __builtin_neon_vcvth_s16_f16(__s0); \ __ret; \ }) #define vcvth_s32_f16(__p0) __extension__ ({ \ int32_t __ret; \ float16_t __s0 = __p0; \ __ret = (int32_t) __builtin_neon_vcvth_s32_f16(__s0); \ __ret; \ }) #define vcvth_s64_f16(__p0) __extension__ ({ \ int64_t __ret; \ float16_t __s0 = __p0; \ __ret = (int64_t) __builtin_neon_vcvth_s64_f16(__s0); \ __ret; \ }) #define vcvth_u16_f16(__p0) __extension__ ({ \ uint16_t __ret; \ float16_t __s0 = __p0; \ __ret = (uint16_t) __builtin_neon_vcvth_u16_f16(__s0); \ __ret; \ }) #define vcvth_u32_f16(__p0) __extension__ ({ \ uint32_t __ret; \ float16_t __s0 = __p0; \ __ret = (uint32_t) __builtin_neon_vcvth_u32_f16(__s0); \ __ret; \ }) #define vcvth_u64_f16(__p0) __extension__ ({ \ uint64_t __ret; \ float16_t __s0 = __p0; \ __ret = (uint64_t) __builtin_neon_vcvth_u64_f16(__s0); \ __ret; \ }) #define vcvtah_s16_f16(__p0) __extension__ ({ \ int16_t __ret; \ float16_t __s0 = __p0; \ __ret = (int16_t) __builtin_neon_vcvtah_s16_f16(__s0); \ __ret; \ }) #define vcvtah_s32_f16(__p0) __extension__ ({ \ int32_t __ret; \ float16_t __s0 = __p0; \ __ret = (int32_t) __builtin_neon_vcvtah_s32_f16(__s0); \ __ret; \ }) #define vcvtah_s64_f16(__p0) __extension__ ({ \ int64_t __ret; \ float16_t __s0 = __p0; \ __ret = (int64_t) __builtin_neon_vcvtah_s64_f16(__s0); \ __ret; \ }) #define vcvtah_u16_f16(__p0) __extension__ ({ \ uint16_t __ret; \ float16_t __s0 = __p0; \ __ret = (uint16_t) __builtin_neon_vcvtah_u16_f16(__s0); \ __ret; \ }) #define vcvtah_u32_f16(__p0) __extension__ ({ \ uint32_t __ret; \ float16_t __s0 = __p0; \ __ret = (uint32_t) __builtin_neon_vcvtah_u32_f16(__s0); \ __ret; \ }) #define vcvtah_u64_f16(__p0) __extension__ ({ \ uint64_t __ret; \ float16_t __s0 = __p0; \ __ret = (uint64_t) __builtin_neon_vcvtah_u64_f16(__s0); \ __ret; \ }) #define vcvth_f16_u16(__p0) __extension__ ({ \ float16_t __ret; \ uint16_t __s0 = __p0; \ __ret = (float16_t) __builtin_neon_vcvth_f16_u16(__s0); \ __ret; \ }) #define vcvth_f16_s16(__p0) __extension__ ({ \ float16_t __ret; \ int16_t __s0 = __p0; \ __ret = (float16_t) __builtin_neon_vcvth_f16_s16(__s0); \ __ret; \ }) #define vcvth_f16_u32(__p0) __extension__ ({ \ float16_t __ret; \ uint32_t __s0 = __p0; \ __ret = (float16_t) __builtin_neon_vcvth_f16_u32(__s0); \ __ret; \ }) #define vcvth_f16_s32(__p0) __extension__ ({ \ float16_t __ret; \ int32_t __s0 = __p0; \ __ret = (float16_t) __builtin_neon_vcvth_f16_s32(__s0); \ __ret; \ }) #define vcvth_f16_u64(__p0) __extension__ ({ \ float16_t __ret; \ uint64_t __s0 = __p0; \ __ret = (float16_t) __builtin_neon_vcvth_f16_u64(__s0); \ __ret; \ }) #define vcvth_f16_s64(__p0) __extension__ ({ \ float16_t __ret; \ int64_t __s0 = __p0; \ __ret = (float16_t) __builtin_neon_vcvth_f16_s64(__s0); \ __ret; \ }) #define vcvth_n_f16_u32(__p0, __p1) __extension__ ({ \ float16_t __ret; \ uint32_t __s0 = __p0; \ __ret = (float16_t) __builtin_neon_vcvth_n_f16_u32(__s0, __p1); \ __ret; \ }) #define vcvth_n_f16_s32(__p0, __p1) __extension__ ({ \ float16_t __ret; \ int32_t __s0 = __p0; \ __ret = (float16_t) __builtin_neon_vcvth_n_f16_s32(__s0, __p1); \ __ret; \ }) #define vcvth_n_f16_u64(__p0, __p1) __extension__ ({ \ float16_t __ret; \ uint64_t __s0 = __p0; \ __ret = (float16_t) __builtin_neon_vcvth_n_f16_u64(__s0, __p1); \ __ret; \ }) #define vcvth_n_f16_s64(__p0, __p1) __extension__ ({ \ float16_t __ret; \ int64_t __s0 = __p0; \ __ret = (float16_t) __builtin_neon_vcvth_n_f16_s64(__s0, __p1); \ __ret; \ }) #define vcvth_n_f16_u16(__p0, __p1) __extension__ ({ \ float16_t __ret; \ uint16_t __s0 = __p0; \ __ret = (float16_t) __builtin_neon_vcvth_n_f16_u16(__s0, __p1); \ __ret; \ }) #define vcvth_n_f16_s16(__p0, __p1) __extension__ ({ \ float16_t __ret; \ int16_t __s0 = __p0; \ __ret = (float16_t) __builtin_neon_vcvth_n_f16_s16(__s0, __p1); \ __ret; \ }) #define vcvtmh_s16_f16(__p0) __extension__ ({ \ int16_t __ret; \ float16_t __s0 = __p0; \ __ret = (int16_t) __builtin_neon_vcvtmh_s16_f16(__s0); \ __ret; \ }) #define vcvtmh_s32_f16(__p0) __extension__ ({ \ int32_t __ret; \ float16_t __s0 = __p0; \ __ret = (int32_t) __builtin_neon_vcvtmh_s32_f16(__s0); \ __ret; \ }) #define vcvtmh_s64_f16(__p0) __extension__ ({ \ int64_t __ret; \ float16_t __s0 = __p0; \ __ret = (int64_t) __builtin_neon_vcvtmh_s64_f16(__s0); \ __ret; \ }) #define vcvtmh_u16_f16(__p0) __extension__ ({ \ uint16_t __ret; \ float16_t __s0 = __p0; \ __ret = (uint16_t) __builtin_neon_vcvtmh_u16_f16(__s0); \ __ret; \ }) #define vcvtmh_u32_f16(__p0) __extension__ ({ \ uint32_t __ret; \ float16_t __s0 = __p0; \ __ret = (uint32_t) __builtin_neon_vcvtmh_u32_f16(__s0); \ __ret; \ }) #define vcvtmh_u64_f16(__p0) __extension__ ({ \ uint64_t __ret; \ float16_t __s0 = __p0; \ __ret = (uint64_t) __builtin_neon_vcvtmh_u64_f16(__s0); \ __ret; \ }) #define vcvtnh_s16_f16(__p0) __extension__ ({ \ int16_t __ret; \ float16_t __s0 = __p0; \ __ret = (int16_t) __builtin_neon_vcvtnh_s16_f16(__s0); \ __ret; \ }) #define vcvtnh_s32_f16(__p0) __extension__ ({ \ int32_t __ret; \ float16_t __s0 = __p0; \ __ret = (int32_t) __builtin_neon_vcvtnh_s32_f16(__s0); \ __ret; \ }) #define vcvtnh_s64_f16(__p0) __extension__ ({ \ int64_t __ret; \ float16_t __s0 = __p0; \ __ret = (int64_t) __builtin_neon_vcvtnh_s64_f16(__s0); \ __ret; \ }) #define vcvtnh_u16_f16(__p0) __extension__ ({ \ uint16_t __ret; \ float16_t __s0 = __p0; \ __ret = (uint16_t) __builtin_neon_vcvtnh_u16_f16(__s0); \ __ret; \ }) #define vcvtnh_u32_f16(__p0) __extension__ ({ \ uint32_t __ret; \ float16_t __s0 = __p0; \ __ret = (uint32_t) __builtin_neon_vcvtnh_u32_f16(__s0); \ __ret; \ }) #define vcvtnh_u64_f16(__p0) __extension__ ({ \ uint64_t __ret; \ float16_t __s0 = __p0; \ __ret = (uint64_t) __builtin_neon_vcvtnh_u64_f16(__s0); \ __ret; \ }) #define vcvtph_s16_f16(__p0) __extension__ ({ \ int16_t __ret; \ float16_t __s0 = __p0; \ __ret = (int16_t) __builtin_neon_vcvtph_s16_f16(__s0); \ __ret; \ }) #define vcvtph_s32_f16(__p0) __extension__ ({ \ int32_t __ret; \ float16_t __s0 = __p0; \ __ret = (int32_t) __builtin_neon_vcvtph_s32_f16(__s0); \ __ret; \ }) #define vcvtph_s64_f16(__p0) __extension__ ({ \ int64_t __ret; \ float16_t __s0 = __p0; \ __ret = (int64_t) __builtin_neon_vcvtph_s64_f16(__s0); \ __ret; \ }) #define vcvtph_u16_f16(__p0) __extension__ ({ \ uint16_t __ret; \ float16_t __s0 = __p0; \ __ret = (uint16_t) __builtin_neon_vcvtph_u16_f16(__s0); \ __ret; \ }) #define vcvtph_u32_f16(__p0) __extension__ ({ \ uint32_t __ret; \ float16_t __s0 = __p0; \ __ret = (uint32_t) __builtin_neon_vcvtph_u32_f16(__s0); \ __ret; \ }) #define vcvtph_u64_f16(__p0) __extension__ ({ \ uint64_t __ret; \ float16_t __s0 = __p0; \ __ret = (uint64_t) __builtin_neon_vcvtph_u64_f16(__s0); \ __ret; \ }) #define vdivh_f16(__p0, __p1) __extension__ ({ \ float16_t __ret; \ float16_t __s0 = __p0; \ float16_t __s1 = __p1; \ __ret = (float16_t) __builtin_neon_vdivh_f16(__s0, __s1); \ __ret; \ }) #define vfmah_f16(__p0, __p1, __p2) __extension__ ({ \ float16_t __ret; \ float16_t __s0 = __p0; \ float16_t __s1 = __p1; \ float16_t __s2 = __p2; \ __ret = (float16_t) __builtin_neon_vfmah_f16(__s0, __s1, __s2); \ __ret; \ }) #define vfmsh_f16(__p0, __p1, __p2) __extension__ ({ \ float16_t __ret; \ float16_t __s0 = __p0; \ float16_t __s1 = __p1; \ float16_t __s2 = __p2; \ __ret = (float16_t) __builtin_neon_vfmsh_f16(__s0, __s1, __s2); \ __ret; \ }) #define vmaxh_f16(__p0, __p1) __extension__ ({ \ float16_t __ret; \ float16_t __s0 = __p0; \ float16_t __s1 = __p1; \ __ret = (float16_t) __builtin_neon_vmaxh_f16(__s0, __s1); \ __ret; \ }) #define vmaxnmh_f16(__p0, __p1) __extension__ ({ \ float16_t __ret; \ float16_t __s0 = __p0; \ float16_t __s1 = __p1; \ __ret = (float16_t) __builtin_neon_vmaxnmh_f16(__s0, __s1); \ __ret; \ }) #define vminh_f16(__p0, __p1) __extension__ ({ \ float16_t __ret; \ float16_t __s0 = __p0; \ float16_t __s1 = __p1; \ __ret = (float16_t) __builtin_neon_vminh_f16(__s0, __s1); \ __ret; \ }) #define vminnmh_f16(__p0, __p1) __extension__ ({ \ float16_t __ret; \ float16_t __s0 = __p0; \ float16_t __s1 = __p1; \ __ret = (float16_t) __builtin_neon_vminnmh_f16(__s0, __s1); \ __ret; \ }) #define vmulh_f16(__p0, __p1) __extension__ ({ \ float16_t __ret; \ float16_t __s0 = __p0; \ float16_t __s1 = __p1; \ __ret = (float16_t) __builtin_neon_vmulh_f16(__s0, __s1); \ __ret; \ }) #define vmulxh_f16(__p0, __p1) __extension__ ({ \ float16_t __ret; \ float16_t __s0 = __p0; \ float16_t __s1 = __p1; \ __ret = (float16_t) __builtin_neon_vmulxh_f16(__s0, __s1); \ __ret; \ }) #define vnegh_f16(__p0) __extension__ ({ \ float16_t __ret; \ float16_t __s0 = __p0; \ __ret = (float16_t) __builtin_neon_vnegh_f16(__s0); \ __ret; \ }) #define vrecpeh_f16(__p0) __extension__ ({ \ float16_t __ret; \ float16_t __s0 = __p0; \ __ret = (float16_t) __builtin_neon_vrecpeh_f16(__s0); \ __ret; \ }) #define vrecpsh_f16(__p0, __p1) __extension__ ({ \ float16_t __ret; \ float16_t __s0 = __p0; \ float16_t __s1 = __p1; \ __ret = (float16_t) __builtin_neon_vrecpsh_f16(__s0, __s1); \ __ret; \ }) #define vrecpxh_f16(__p0) __extension__ ({ \ float16_t __ret; \ float16_t __s0 = __p0; \ __ret = (float16_t) __builtin_neon_vrecpxh_f16(__s0); \ __ret; \ }) #define vrndh_f16(__p0) __extension__ ({ \ float16_t __ret; \ float16_t __s0 = __p0; \ __ret = (float16_t) __builtin_neon_vrndh_f16(__s0); \ __ret; \ }) #define vrndah_f16(__p0) __extension__ ({ \ float16_t __ret; \ float16_t __s0 = __p0; \ __ret = (float16_t) __builtin_neon_vrndah_f16(__s0); \ __ret; \ }) #define vrndih_f16(__p0) __extension__ ({ \ float16_t __ret; \ float16_t __s0 = __p0; \ __ret = (float16_t) __builtin_neon_vrndih_f16(__s0); \ __ret; \ }) #define vrndmh_f16(__p0) __extension__ ({ \ float16_t __ret; \ float16_t __s0 = __p0; \ __ret = (float16_t) __builtin_neon_vrndmh_f16(__s0); \ __ret; \ }) #define vrndnh_f16(__p0) __extension__ ({ \ float16_t __ret; \ float16_t __s0 = __p0; \ __ret = (float16_t) __builtin_neon_vrndnh_f16(__s0); \ __ret; \ }) #define vrndph_f16(__p0) __extension__ ({ \ float16_t __ret; \ float16_t __s0 = __p0; \ __ret = (float16_t) __builtin_neon_vrndph_f16(__s0); \ __ret; \ }) #define vrndxh_f16(__p0) __extension__ ({ \ float16_t __ret; \ float16_t __s0 = __p0; \ __ret = (float16_t) __builtin_neon_vrndxh_f16(__s0); \ __ret; \ }) #define vrsqrteh_f16(__p0) __extension__ ({ \ float16_t __ret; \ float16_t __s0 = __p0; \ __ret = (float16_t) __builtin_neon_vrsqrteh_f16(__s0); \ __ret; \ }) #define vrsqrtsh_f16(__p0, __p1) __extension__ ({ \ float16_t __ret; \ float16_t __s0 = __p0; \ float16_t __s1 = __p1; \ __ret = (float16_t) __builtin_neon_vrsqrtsh_f16(__s0, __s1); \ __ret; \ }) #define vsqrth_f16(__p0) __extension__ ({ \ float16_t __ret; \ float16_t __s0 = __p0; \ __ret = (float16_t) __builtin_neon_vsqrth_f16(__s0); \ __ret; \ }) #define vsubh_f16(__p0, __p1) __extension__ ({ \ float16_t __ret; \ float16_t __s0 = __p0; \ float16_t __s1 = __p1; \ __ret = (float16_t) __builtin_neon_vsubh_f16(__s0, __s1); \ __ret; \ }) #endif #undef __ai #endif /* __ARM_FP16_H */