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Name	Size	Permission	Date
cuda_wrappers	[ DIR ]	drwxr-xr-x	2026-02-03 15:09
fuzzer	[ DIR ]	drwxr-xr-x	2026-02-03 15:08
llvm_libc_wrappers	[ DIR ]	drwxr-xr-x	2026-02-03 15:09
llvm_offload_wrappers	[ DIR ]	drwxr-xr-x	2026-02-03 15:09
openmp_wrappers	[ DIR ]	drwxr-xr-x	2026-02-03 15:09
orc	[ DIR ]	drwxr-xr-x	2026-02-03 15:08
ppc_wrappers	[ DIR ]	drwxr-xr-x	2026-02-03 15:09
profile	[ DIR ]	drwxr-xr-x	2026-02-03 15:08
sanitizer	[ DIR ]	drwxr-xr-x	2026-02-03 15:08
xray	[ DIR ]	drwxr-xr-x	2026-02-03 15:08
zos_wrappers	[ DIR ]	drwxr-xr-x	2026-02-03 15:09
__clang_cuda_builtin_vars.h	4.78 KB	-rw-r--r--	2025-07-08 23:06
__clang_cuda_cmath.h	18.06 KB	-rw-r--r--	2025-07-08 23:06
__clang_cuda_complex_builtins.h	9.36 KB	-rw-r--r--	2025-07-08 23:06
__clang_cuda_device_functions.h	57.36 KB	-rw-r--r--	2025-07-08 23:06
__clang_cuda_intrinsics.h	29.87 KB	-rw-r--r--	2025-07-08 23:06
__clang_cuda_libdevice_declares.h	21.89 KB	-rw-r--r--	2025-07-08 23:06
__clang_cuda_math.h	16.21 KB	-rw-r--r--	2025-07-08 23:06
__clang_cuda_math_forward_declares.h	8.27 KB	-rw-r--r--	2025-07-08 23:06
__clang_cuda_runtime_wrapper.h	17.6 KB	-rw-r--r--	2025-07-08 23:06
__clang_cuda_texture_intrinsics.h	31.86 KB	-rw-r--r--	2025-07-08 23:06
__clang_hip_cmath.h	26.48 KB	-rw-r--r--	2025-07-08 23:06
__clang_hip_libdevice_declares.h	19.87 KB	-rw-r--r--	2025-07-08 23:06
__clang_hip_math.h	32.78 KB	-rw-r--r--	2025-07-08 23:06
__clang_hip_runtime_wrapper.h	4.94 KB	-rw-r--r--	2025-07-08 23:06
__clang_hip_stdlib.h	1.19 KB	-rw-r--r--	2025-07-08 23:06
__stdarg___gnuc_va_list.h	467 B	-rw-r--r--	2025-07-08 23:06
__stdarg___va_copy.h	445 B	-rw-r--r--	2025-07-08 23:06
__stdarg_header_macro.h	417 B	-rw-r--r--	2025-07-08 23:06
__stdarg_va_arg.h	793 B	-rw-r--r--	2025-07-08 23:06
__stdarg_va_copy.h	451 B	-rw-r--r--	2025-07-08 23:06
__stdarg_va_list.h	448 B	-rw-r--r--	2025-07-08 23:06
__stddef_header_macro.h	417 B	-rw-r--r--	2025-07-08 23:06
__stddef_max_align_t.h	857 B	-rw-r--r--	2025-07-08 23:06
__stddef_null.h	875 B	-rw-r--r--	2025-07-08 23:06
__stddef_nullptr_t.h	958 B	-rw-r--r--	2025-07-08 23:06
__stddef_offsetof.h	708 B	-rw-r--r--	2025-07-08 23:06
__stddef_ptrdiff_t.h	717 B	-rw-r--r--	2025-07-08 23:06
__stddef_rsize_t.h	710 B	-rw-r--r--	2025-07-08 23:06
__stddef_size_t.h	708 B	-rw-r--r--	2025-07-08 23:06
__stddef_unreachable.h	735 B	-rw-r--r--	2025-07-08 23:06
__stddef_wchar_t.h	853 B	-rw-r--r--	2025-07-08 23:06
__stddef_wint_t.h	443 B	-rw-r--r--	2025-07-08 23:06
__wmmintrin_aes.h	5.15 KB	-rw-r--r--	2025-07-08 23:06
__wmmintrin_pclmul.h	1.99 KB	-rw-r--r--	2025-07-08 23:06
adcintrin.h	5.43 KB	-rw-r--r--	2025-07-08 23:06
adxintrin.h	3.37 KB	-rw-r--r--	2025-07-08 23:06
altivec.h	698.45 KB	-rw-r--r--	2025-07-08 23:06
amdgpuintrin.h	7.4 KB	-rw-r--r--	2025-07-08 23:06
ammintrin.h	7.56 KB	-rw-r--r--	2025-07-08 23:06
amxavx512intrin.h	12.67 KB	-rw-r--r--	2025-07-08 23:06
amxbf16transposeintrin.h	3.44 KB	-rw-r--r--	2025-07-08 23:06
amxcomplexintrin.h	6.81 KB	-rw-r--r--	2025-07-08 23:06
amxcomplextransposeintrin.h	11.78 KB	-rw-r--r--	2025-07-08 23:06
amxfp16intrin.h	3.25 KB	-rw-r--r--	2025-07-08 23:06
amxfp16transposeintrin.h	3.44 KB	-rw-r--r--	2025-07-08 23:06
amxfp8intrin.h	8.63 KB	-rw-r--r--	2025-07-08 23:06
amxintrin.h	19.83 KB	-rw-r--r--	2025-07-08 23:06
amxmovrsintrin.h	2.24 KB	-rw-r--r--	2025-07-08 23:06
amxmovrstransposeintrin.h	9.18 KB	-rw-r--r--	2025-07-08 23:06
amxtf32intrin.h	3.48 KB	-rw-r--r--	2025-07-08 23:06
amxtf32transposeintrin.h	3.56 KB	-rw-r--r--	2025-07-08 23:06
amxtransposeintrin.h	10.6 KB	-rw-r--r--	2025-07-08 23:06
arm64intr.h	993 B	-rw-r--r--	2025-07-08 23:06
arm_acle.h	29.97 KB	-rw-r--r--	2025-07-08 23:06
arm_bf16.h	548 B	-rw-r--r--	2025-09-17 20:10
arm_cde.h	32.67 KB	-rw-r--r--	2025-09-17 20:10
arm_cmse.h	6.21 KB	-rw-r--r--	2025-07-08 23:06
arm_fp16.h	16.94 KB	-rw-r--r--	2025-09-17 20:10
arm_mve.h	1.48 MB	-rw-r--r--	2025-09-17 20:10
arm_neon.h	2.66 MB	-rw-r--r--	2025-09-17 20:10
arm_neon_sve_bridge.h	9.48 KB	-rw-r--r--	2025-07-08 23:06
arm_sme.h	223.36 KB	-rw-r--r--	2025-09-17 20:10
arm_sve.h	2.03 MB	-rw-r--r--	2025-09-17 20:10
arm_vector_types.h	9.86 KB	-rw-r--r--	2025-09-17 20:10
armintr.h	843 B	-rw-r--r--	2025-07-08 23:06
avx10_2_512bf16intrin.h	22.87 KB	-rw-r--r--	2025-07-08 23:06
avx10_2_512convertintrin.h	12.88 KB	-rw-r--r--	2025-07-08 23:06
avx10_2_512minmaxintrin.h	7.35 KB	-rw-r--r--	2025-07-08 23:06
avx10_2_512niintrin.h	13.71 KB	-rw-r--r--	2025-07-08 23:06
avx10_2_512satcvtdsintrin.h	13.48 KB	-rw-r--r--	2025-07-08 23:06
avx10_2_512satcvtintrin.h	16.6 KB	-rw-r--r--	2025-07-08 23:06
avx10_2bf16intrin.h	43.63 KB	-rw-r--r--	2025-07-08 23:06
avx10_2convertintrin.h	22.75 KB	-rw-r--r--	2025-07-08 23:06
avx10_2copyintrin.h	2.35 KB	-rw-r--r--	2025-07-08 23:06
avx10_2minmaxintrin.h	13.53 KB	-rw-r--r--	2025-07-08 23:06
avx10_2niintrin.h	16.6 KB	-rw-r--r--	2025-07-08 23:06
avx10_2satcvtdsintrin.h	15.36 KB	-rw-r--r--	2025-07-08 23:06
avx10_2satcvtintrin.h	18.87 KB	-rw-r--r--	2025-07-08 23:06
avx2intrin.h	188.12 KB	-rw-r--r--	2025-07-08 23:06
avx512bf16intrin.h	10.58 KB	-rw-r--r--	2025-07-08 23:06
avx512bitalgintrin.h	2.56 KB	-rw-r--r--	2025-07-08 23:06
avx512bwintrin.h	76.02 KB	-rw-r--r--	2025-07-08 23:06
avx512cdintrin.h	4.23 KB	-rw-r--r--	2025-07-08 23:06
avx512dqintrin.h	58.87 KB	-rw-r--r--	2025-07-08 23:06
avx512fintrin.h	383.45 KB	-rw-r--r--	2025-07-08 23:06
avx512fp16intrin.h	156.92 KB	-rw-r--r--	2025-07-08 23:06
avx512ifmaintrin.h	2.6 KB	-rw-r--r--	2025-07-08 23:06
avx512ifmavlintrin.h	4.6 KB	-rw-r--r--	2025-07-08 23:06
avx512vbmi2intrin.h	13.18 KB	-rw-r--r--	2025-07-08 23:06
avx512vbmiintrin.h	3.83 KB	-rw-r--r--	2025-07-08 23:06
avx512vbmivlintrin.h	7.23 KB	-rw-r--r--	2025-07-08 23:06
avx512vlbf16intrin.h	19.46 KB	-rw-r--r--	2025-07-08 23:06
avx512vlbitalgintrin.h	4.52 KB	-rw-r--r--	2025-07-08 23:06
avx512vlbwintrin.h	121.56 KB	-rw-r--r--	2025-07-08 23:06
avx512vlcdintrin.h	7.95 KB	-rw-r--r--	2025-07-08 23:06
avx512vldqintrin.h	46.71 KB	-rw-r--r--	2025-07-08 23:06
avx512vlfp16intrin.h	85.51 KB	-rw-r--r--	2025-07-08 23:06
avx512vlintrin.h	322.6 KB	-rw-r--r--	2025-07-08 23:06
avx512vlvbmi2intrin.h	26.01 KB	-rw-r--r--	2025-07-08 23:06
avx512vlvnniintrin.h	13.41 KB	-rw-r--r--	2025-07-08 23:06
avx512vlvp2intersectintrin.h	4.67 KB	-rw-r--r--	2025-07-08 23:06
avx512vnniintrin.h	4.32 KB	-rw-r--r--	2025-07-08 23:06
avx512vp2intersectintrin.h	3.03 KB	-rw-r--r--	2025-07-08 23:06
avx512vpopcntdqintrin.h	2.3 KB	-rw-r--r--	2025-07-08 23:06
avx512vpopcntdqvlintrin.h	3.86 KB	-rw-r--r--	2025-07-08 23:06
avxifmaintrin.h	5.75 KB	-rw-r--r--	2025-07-08 23:06
avxintrin.h	197.12 KB	-rw-r--r--	2025-07-08 23:06
avxneconvertintrin.h	14.09 KB	-rw-r--r--	2025-07-08 23:06
avxvnniint16intrin.h	15.84 KB	-rw-r--r--	2025-07-08 23:06
avxvnniint8intrin.h	17.02 KB	-rw-r--r--	2025-07-08 23:06
avxvnniintrin.h	10.44 KB	-rw-r--r--	2025-07-08 23:06
bmi2intrin.h	7.37 KB	-rw-r--r--	2025-07-08 23:06
bmiintrin.h	20.02 KB	-rw-r--r--	2025-07-08 23:06
builtins.h	846 B	-rw-r--r--	2025-07-08 23:06
cet.h	1.49 KB	-rw-r--r--	2025-07-08 23:06
cetintrin.h	3.27 KB	-rw-r--r--	2025-07-08 23:06
cldemoteintrin.h	1.18 KB	-rw-r--r--	2025-07-08 23:06
clflushoptintrin.h	1.17 KB	-rw-r--r--	2025-07-08 23:06
clwbintrin.h	1.2 KB	-rw-r--r--	2025-07-08 23:06
clzerointrin.h	1.19 KB	-rw-r--r--	2025-07-08 23:06
cmpccxaddintrin.h	2.33 KB	-rw-r--r--	2025-07-08 23:06
cpuid.h	11.9 KB	-rw-r--r--	2025-07-08 23:06
crc32intrin.h	3.27 KB	-rw-r--r--	2025-07-08 23:06
emmintrin.h	196.89 KB	-rw-r--r--	2025-07-08 23:06
enqcmdintrin.h	2.12 KB	-rw-r--r--	2025-07-08 23:06
f16cintrin.h	5.39 KB	-rw-r--r--	2025-07-08 23:06
float.h	6.43 KB	-rw-r--r--	2025-07-08 23:06
fma4intrin.h	6.82 KB	-rw-r--r--	2025-07-08 23:06
fmaintrin.h	28.65 KB	-rw-r--r--	2025-07-08 23:06
fxsrintrin.h	2.82 KB	-rw-r--r--	2025-07-08 23:06
gfniintrin.h	9.59 KB	-rw-r--r--	2025-07-08 23:06
gpuintrin.h	9.07 KB	-rw-r--r--	2025-07-08 23:06
hexagon_circ_brev_intrinsics.h	15.59 KB	-rw-r--r--	2025-07-08 23:06
hexagon_protos.h	374.42 KB	-rw-r--r--	2025-07-08 23:06
hexagon_types.h	130.38 KB	-rw-r--r--	2025-07-08 23:06
hresetintrin.h	1.36 KB	-rw-r--r--	2025-07-08 23:06
htmintrin.h	6.14 KB	-rw-r--r--	2025-07-08 23:06
htmxlintrin.h	9.01 KB	-rw-r--r--	2025-07-08 23:06
hvx_hexagon_protos.h	275.18 KB	-rw-r--r--	2025-07-08 23:06
ia32intrin.h	25.38 KB	-rw-r--r--	2025-07-08 23:06
immintrin.h	25.46 KB	-rw-r--r--	2025-07-08 23:06
intrin.h	18.16 KB	-rw-r--r--	2025-07-08 23:06
intrin0.h	13.76 KB	-rw-r--r--	2025-07-08 23:06
inttypes.h	2.37 KB	-rw-r--r--	2025-07-08 23:06
invpcidintrin.h	764 B	-rw-r--r--	2025-07-08 23:06
iso646.h	763 B	-rw-r--r--	2025-07-08 23:06
keylockerintrin.h	17.85 KB	-rw-r--r--	2025-07-08 23:06
larchintrin.h	8.5 KB	-rw-r--r--	2025-07-08 23:06
lasxintrin.h	142.14 KB	-rw-r--r--	2025-07-08 23:06
limits.h	3.71 KB	-rw-r--r--	2025-07-08 23:06
lsxintrin.h	134.7 KB	-rw-r--r--	2025-07-08 23:06
lwpintrin.h	5 KB	-rw-r--r--	2025-07-08 23:06
lzcntintrin.h	3.45 KB	-rw-r--r--	2025-07-08 23:06
mm3dnow.h	729 B	-rw-r--r--	2025-07-08 23:06
mm_malloc.h	1.88 KB	-rw-r--r--	2025-07-08 23:06
mmintrin.h	58.6 KB	-rw-r--r--	2025-07-08 23:06
module.modulemap	6.47 KB	-rw-r--r--	2025-07-08 23:06
movdirintrin.h	1.57 KB	-rw-r--r--	2025-07-08 23:06
movrs_avx10_2_512intrin.h	3.88 KB	-rw-r--r--	2025-07-08 23:06
movrs_avx10_2intrin.h	6.87 KB	-rw-r--r--	2025-07-08 23:06
movrsintrin.h	1.98 KB	-rw-r--r--	2025-07-08 23:06
msa.h	25.01 KB	-rw-r--r--	2025-07-08 23:06
mwaitxintrin.h	2.19 KB	-rw-r--r--	2025-07-08 23:06
nmmintrin.h	709 B	-rw-r--r--	2025-07-08 23:06
nvptxintrin.h	7.42 KB	-rw-r--r--	2025-07-08 23:06
omp-tools.h	50.86 KB	-rw-r--r--	2025-09-17 20:37
omp.h	23.36 KB	-rw-r--r--	2025-09-17 20:37
ompt-multiplex.h	51.11 KB	-rw-r--r--	2025-07-08 23:06
ompt.h	50.86 KB	-rw-r--r--	2025-09-17 20:37
ompx.h	7.38 KB	-rw-r--r--	2025-09-17 20:37
opencl-c-base.h	30.94 KB	-rw-r--r--	2025-07-08 23:06
opencl-c.h	874.98 KB	-rw-r--r--	2025-07-08 23:06
pconfigintrin.h	1.19 KB	-rw-r--r--	2025-07-08 23:06
pkuintrin.h	934 B	-rw-r--r--	2025-07-08 23:06
pmmintrin.h	11.12 KB	-rw-r--r--	2025-07-08 23:06
popcntintrin.h	1.9 KB	-rw-r--r--	2025-07-08 23:06
prfchiintrin.h	2.02 KB	-rw-r--r--	2025-07-08 23:06
prfchwintrin.h	2.06 KB	-rw-r--r--	2025-07-08 23:06
ptrauth.h	15.61 KB	-rw-r--r--	2025-07-08 23:06
ptwriteintrin.h	1.05 KB	-rw-r--r--	2025-07-08 23:06
raointintrin.h	6.59 KB	-rw-r--r--	2025-07-08 23:06
rdpruintrin.h	1.59 KB	-rw-r--r--	2025-07-08 23:06
rdseedintrin.h	2.85 KB	-rw-r--r--	2025-07-08 23:06
riscv_bitmanip.h	5.59 KB	-rw-r--r--	2025-07-08 23:06
riscv_corev_alu.h	3.94 KB	-rw-r--r--	2025-07-08 23:06
riscv_crypto.h	5.09 KB	-rw-r--r--	2025-07-08 23:06
riscv_ntlh.h	744 B	-rw-r--r--	2025-07-08 23:06
riscv_vector.h	17.11 KB	-rw-r--r--	2025-09-17 20:11
rtmintrin.h	1.25 KB	-rw-r--r--	2025-07-08 23:06
s390intrin.h	604 B	-rw-r--r--	2025-07-08 23:06
serializeintrin.h	881 B	-rw-r--r--	2025-07-08 23:06
sgxintrin.h	1.77 KB	-rw-r--r--	2025-07-08 23:06
sha512intrin.h	5.95 KB	-rw-r--r--	2025-07-08 23:06
shaintrin.h	7.37 KB	-rw-r--r--	2025-07-08 23:06
sifive_vector.h	6.88 KB	-rw-r--r--	2025-07-08 23:06
sm3intrin.h	7.29 KB	-rw-r--r--	2025-07-08 23:06
sm4evexintrin.h	1.17 KB	-rw-r--r--	2025-07-08 23:06
sm4intrin.h	8.2 KB	-rw-r--r--	2025-07-08 23:06
smmintrin.h	99.34 KB	-rw-r--r--	2025-07-08 23:06
stdalign.h	756 B	-rw-r--r--	2025-07-08 23:06
stdarg.h	2.44 KB	-rw-r--r--	2025-07-08 23:06
stdatomic.h	8.46 KB	-rw-r--r--	2025-07-08 23:06
stdbool.h	1.14 KB	-rw-r--r--	2025-07-08 23:06
stdckdint.h	1.63 KB	-rw-r--r--	2025-07-08 23:06
stddef.h	4.93 KB	-rw-r--r--	2025-07-08 23:06
stdint.h	30.33 KB	-rw-r--r--	2025-07-08 23:06
stdnoreturn.h	1.29 KB	-rw-r--r--	2025-07-08 23:06
tbmintrin.h	3.42 KB	-rw-r--r--	2025-07-08 23:06
tgmath.h	29.68 KB	-rw-r--r--	2025-07-08 23:06
tmmintrin.h	31.18 KB	-rw-r--r--	2025-07-08 23:06
tsxldtrkintrin.h	1.97 KB	-rw-r--r--	2025-07-08 23:06
uintrintrin.h	4.96 KB	-rw-r--r--	2025-07-08 23:06
unwind.h	11.21 KB	-rw-r--r--	2025-07-08 23:06
usermsrintrin.h	1.54 KB	-rw-r--r--	2025-07-08 23:06
vadefs.h	1.39 KB	-rw-r--r--	2025-07-08 23:06
vaesintrin.h	2.61 KB	-rw-r--r--	2025-07-08 23:06
varargs.h	584 B	-rw-r--r--	2025-07-08 23:06
vecintrin.h	419.23 KB	-rw-r--r--	2025-07-08 23:06
velintrin.h	2.1 KB	-rw-r--r--	2025-07-08 23:06
velintrin_approx.h	3.54 KB	-rw-r--r--	2025-07-08 23:06
velintrin_gen.h	69.06 KB	-rw-r--r--	2025-07-08 23:06
vpclmulqdqintrin.h	1.06 KB	-rw-r--r--	2025-07-08 23:06
waitpkgintrin.h	1.33 KB	-rw-r--r--	2025-07-08 23:06
wasm_simd128.h	81.71 KB	-rw-r--r--	2025-07-08 23:06
wbnoinvdintrin.h	749 B	-rw-r--r--	2025-07-08 23:06
wmmintrin.h	659 B	-rw-r--r--	2025-07-08 23:06
x86gprintrin.h	2.22 KB	-rw-r--r--	2025-07-08 23:06
x86intrin.h	1.38 KB	-rw-r--r--	2025-07-08 23:06
xmmintrin.h	117.43 KB	-rw-r--r--	2025-07-08 23:06
xopintrin.h	19.96 KB	-rw-r--r--	2025-07-08 23:06
xsavecintrin.h	2.51 KB	-rw-r--r--	2025-07-08 23:06
xsaveintrin.h	1.64 KB	-rw-r--r--	2025-07-08 23:06
xsaveoptintrin.h	1 KB	-rw-r--r--	2025-07-08 23:06
xsavesintrin.h	1.24 KB	-rw-r--r--	2025-07-08 23:06
xtestintrin.h	873 B	-rw-r--r--	2025-07-08 23:06
yvals_core.h	687 B	-rw-r--r--	2025-07-08 23:06

Rename

/*===-------------------- sm3intrin.h - SM3 intrinsics ---------------------===
 *
 * Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 * See https://llvm.org/LICENSE.txt for license information.
 * SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 *
 *===-----------------------------------------------------------------------===
 */

#ifndef __IMMINTRIN_H
#error "Never use <sm3intrin.h> directly; include <immintrin.h> instead."
#endif // __IMMINTRIN_H

#ifndef __SM3INTRIN_H
#define __SM3INTRIN_H

#define __DEFAULT_FN_ATTRS128                                                  \
  __attribute__((__always_inline__, __nodebug__, __target__("sm3"),            \
                 __min_vector_width__(128)))

/// This intrinisc is one of the two SM3 message scheduling intrinsics. The
///    intrinsic performs an initial calculation for the next four SM3 message
///    words. The calculated results are stored in \a dst.
///
/// \headerfile <immintrin.h>
///
/// \code
/// __m128i _mm_sm3msg1_epi32(__m128i __A, __m128i __B, __m128i __C)
/// \endcode
///
/// This intrinsic corresponds to the \c VSM3MSG1 instruction.
///
/// \param __A
///    A 128-bit vector of [4 x int].
/// \param __B
///    A 128-bit vector of [4 x int].
/// \param __C
///    A 128-bit vector of [4 x int].
/// \returns
///    A 128-bit vector of [4 x int].
///
/// \code{.operation}
/// DEFINE ROL32(dword, n) {
/// 	count := n % 32
/// 	dest := (dword << count) | (dword >> (32 - count))
/// 	RETURN dest
/// }
/// DEFINE P1(x) {
/// 	RETURN x ^ ROL32(x, 15) ^ ROL32(x, 23)
/// }
/// W[0] := __C.dword[0]
/// W[1] := __C.dword[1]
/// W[2] := __C.dword[2]
/// W[3] := __C.dword[3]
/// W[7] := __A.dword[0]
/// W[8] := __A.dword[1]
/// W[9] := __A.dword[2]
/// W[10] := __A.dword[3]
/// W[13] := __B.dword[0]
/// W[14] := __B.dword[1]
/// W[15] := __B.dword[2]
/// TMP0 := W[7] ^ W[0] ^ ROL32(W[13], 15)
/// TMP1 := W[8] ^ W[1] ^ ROL32(W[14], 15)
/// TMP2 := W[9] ^ W[2] ^ ROL32(W[15], 15)
/// TMP3 := W[10] ^ W[3]
/// dst.dword[0] := P1(TMP0)
/// dst.dword[1] := P1(TMP1)
/// dst.dword[2] := P1(TMP2)
/// dst.dword[3] := P1(TMP3)
/// dst[MAX:128] := 0
/// \endcode
static __inline__ __m128i __DEFAULT_FN_ATTRS128 _mm_sm3msg1_epi32(__m128i __A,
                                                                  __m128i __B,
                                                                  __m128i __C) {
  return (__m128i)__builtin_ia32_vsm3msg1((__v4su)__A, (__v4su)__B,
                                          (__v4su)__C);
}

/// This intrinisc is one of the two SM3 message scheduling intrinsics. The
///    intrinsic performs the final calculation for the next four SM3 message
///    words. The calculated results are stored in \a dst.
///
/// \headerfile <immintrin.h>
///
/// \code
/// __m128i _mm_sm3msg2_epi32(__m128i __A, __m128i __B, __m128i __C)
/// \endcode
///
/// This intrinsic corresponds to the \c VSM3MSG2 instruction.
///
/// \param __A
///    A 128-bit vector of [4 x int].
/// \param __B
///    A 128-bit vector of [4 x int].
/// \param __C
///    A 128-bit vector of [4 x int].
/// \returns
///    A 128-bit vector of [4 x int].
///
/// \code{.operation}
/// DEFINE ROL32(dword, n) {
/// 	count := n % 32
/// 	dest := (dword << count) | (dword >> (32-count))
/// 	RETURN dest
/// }
/// WTMP[0] := __A.dword[0]
/// WTMP[1] := __A.dword[1]
/// WTMP[2] := __A.dword[2]
/// WTMP[3] := __A.dword[3]
/// W[3] := __B.dword[0]
/// W[4] := __B.dword[1]
/// W[5] := __B.dword[2]
/// W[6] := __B.dword[3]
/// W[10] := __C.dword[0]
/// W[11] := __C.dword[1]
/// W[12] := __C.dword[2]
/// W[13] := __C.dword[3]
/// W[16] := ROL32(W[3], 7) ^ W[10] ^ WTMP[0]
/// W[17] := ROL32(W[4], 7) ^ W[11] ^ WTMP[1]
/// W[18] := ROL32(W[5], 7) ^ W[12] ^ WTMP[2]
/// W[19] := ROL32(W[6], 7) ^ W[13] ^ WTMP[3]
/// W[19] := W[19] ^ ROL32(W[16], 6) ^ ROL32(W[16], 15) ^ ROL32(W[16], 30)
/// dst.dword[0] := W[16]
/// dst.dword[1] := W[17]
/// dst.dword[2] := W[18]
/// dst.dword[3] := W[19]
/// dst[MAX:128] := 0
/// \endcode
static __inline__ __m128i __DEFAULT_FN_ATTRS128 _mm_sm3msg2_epi32(__m128i __A,
                                                                  __m128i __B,
                                                                  __m128i __C) {
  return (__m128i)__builtin_ia32_vsm3msg2((__v4su)__A, (__v4su)__B,
                                          (__v4su)__C);
}

/// This intrinsic performs two rounds of SM3 operation using initial SM3 state
///    (C, D, G, H) from \a __A, an initial SM3 states (A, B, E, F)
///    from \a __B and a pre-computed words from the \a __C. \a __A with
///    initial SM3 state of (C, D, G, H) assumes input of non-rotated left
///    variables from previous state. The updated SM3 state (A, B, E, F) is
///    written to \a __A. The \a imm8 should contain the even round number
///    for the first of the two rounds computed by this instruction. The
///    computation masks the \a imm8 value by AND’ing it with 0x3E so that only
///    even round numbers from 0 through 62 are used for this operation. The
///    calculated results are stored in \a dst.
///
/// \headerfile <immintrin.h>
///
/// \code
/// __m128i _mm_sm3rnds2_epi32(__m128i __A, __m128i __B, __m128i __C, const int
/// imm8) \endcode
///
/// This intrinsic corresponds to the \c VSM3RNDS2 instruction.
///
/// \param __A
///    A 128-bit vector of [4 x int].
/// \param __B
///    A 128-bit vector of [4 x int].
/// \param __C
///    A 128-bit vector of [4 x int].
/// \param imm8
///    A 8-bit constant integer.
/// \returns
///    A 128-bit vector of [4 x int].
///
/// \code{.operation}
/// DEFINE ROL32(dword, n) {
/// 	count := n % 32
/// 	dest := (dword << count) | (dword >> (32-count))
/// 	RETURN dest
/// }
/// DEFINE P0(dword) {
/// 	RETURN dword ^ ROL32(dword, 9) ^ ROL32(dword, 17)
/// }
/// DEFINE FF(x,y,z, round){
/// 	IF round < 16
/// 		RETURN (x ^ y ^ z)
/// 	ELSE
/// 		RETURN (x & y) | (x & z) | (y & z)
/// 	FI
/// }
/// DEFINE GG(x, y, z, round){
///   IF round < 16
///   	RETURN (x ^ y ^ z)
///   ELSE
///   	RETURN (x & y) | (~x & z)
///   FI
/// }
/// A[0] := __B.dword[3]
/// B[0] := __B.dword[2]
/// C[0] := __A.dword[3]
/// D[0] := __A.dword[2]
/// E[0] := __B.dword[1]
/// F[0] := __B.dword[0]
/// G[0] := __A.dword[1]
/// H[0] := __A.dword[0]
/// W[0] := __C.dword[0]
/// W[1] := __C.dword[1]
/// W[4] := __C.dword[2]
/// W[5] := __C.dword[3]
/// C[0] := ROL32(C[0], 9)
/// D[0] := ROL32(D[0], 9)
/// G[0] := ROL32(G[0], 19)
/// H[0] := ROL32(H[0], 19)
/// ROUND := __D & 0x3E
/// IF ROUND < 16
/// 	CONST := 0x79CC4519
/// ELSE
/// 	CONST := 0x7A879D8A
/// FI
/// CONST := ROL32(CONST,ROUND)
/// FOR i:= 0 to 1
/// 	S1 := ROL32((ROL32(A[i], 12) + E[i] + CONST), 7)
/// 	S2 := S1 ^ ROL32(A[i], 12)
/// 	T1 := FF(A[i], B[i], C[i], ROUND) + D[i] + S2 + (W[i] ^ W[i+4])
/// 	T2 := GG(E[i], F[i], G[i], ROUND) + H[i] + S1 + W[i]
/// 	D[i+1] := C[i]
/// 	C[i+1] := ROL32(B[i],9)
/// 	B[i+1] := A[i]
/// 	A[i+1] := T1
/// 	H[i+1] := G[i]
/// 	G[i+1] := ROL32(F[i], 19)
/// 	F[i+1] := E[i]
/// 	E[i+1] := P0(T2)
/// 	CONST := ROL32(CONST, 1)
/// ENDFOR
/// dst.dword[3] := A[2]
/// dst.dword[2] := B[2]
/// dst.dword[1] := E[2]
/// dst.dword[0] := F[2]
/// dst[MAX:128] := 0
/// \endcode
#define _mm_sm3rnds2_epi32(A, B, C, D)                                         \
  (__m128i) __builtin_ia32_vsm3rnds2((__v4su)A, (__v4su)B, (__v4su)C, (int)D)

#undef __DEFAULT_FN_ATTRS128

#endif // __SM3INTRIN_H